The present invention relates to a voltage generator circuit, and more particularly, to a voltage generator circuit built in a semiconductor device.
A semiconductor device may be provided with a voltage generator circuit which receives an external supply voltage to generate an internal supply voltage that is supplied to internal circuits of the semiconductor device.
Employment of a step-down circuit in the voltage generator circuit can accommodate a reduction in gate breakdown and drain-source breakdown resulting from a reduction in power consumption of the internal circuits and miniaturization of transistors. In a semiconductor device intended for installation in a system that has a power-down mode, the operation of the voltage generator circuit is deactivated in the power-down mode to shut off a current consumed in the internal circuits.
FIG. 1 is a schematic circuit diagram of a voltage generator circuit 100 according to a first prior art example. The voltage generator circuit 100 functions as a step-down circuit which includes a plurality of N-channel MOS transistors. A step-down transistor Tr1, comprised of an N-channel MOS transistor, is provided with an external power supply (high potential power supply) Vcc at a drain, and a reference voltage Vg generated by a reference voltage generator circuit (not shown) at the gate.
The step-down transistor Tr1 has a source coupled to an internal circuit 1. When the reference voltage Vg is supplied to the gate of the transistor Tr1, the internal circuit 1 is supplied with an internal voltage (internal supply voltage) Vdd which is reduced by a threshold value Vthn of the transistor Tr1 from the voltage of the external power supply Vcc.
A capacitor C1 is coupled between the gate of the transistor Tr1 and an external power supply (low potential power supply) Vss. The capacitor C1 reduces coupling noise included in the reference voltage Vg in response to fluctuations in the internal voltage Vdd.
A reference voltage clamp transistor Tr2, comprised of an N-channel MOS transistor, is coupled between the gate of the transistor Tr1 and the external power supply Vss. The transistor Tr2 is supplied with a power-down signal pd at the gate. When the power-down signal pd rises to H level in a power-down mode, the transistor Tr2 is turned on to clamp the reference voltage Vg to the voltage of the external power supply Vss, causing the transistor Tr1 to turn off.
A capacitor C2 is coupled between the source of the transistor Tr1 (internal voltage Vdd) and the external power supply Vss. The capacitor C2 is used to stabilize the internal voltage Vdd. The capacitor C2 includes a parasitic capacitance of the internal circuit 1.
An internal voltage clamp transistor Tr3, comprised of an N-channel MOS transistor, is coupled between the source of the transistor Tr1 and the external power supply Vss. The transistor Tr3 is supplied with the power-down signal pd at the gate. When the power-down signal pd rises to H level, the transistor Tr3 is turned on with the transistor Tr1 remaining off, to clamp the internal voltage Vdd to the voltage of the external power supply Vss, as shown in FIG. 3. Such an operation shuts off the supply of the internal voltage Vdd in the power-down mode, so that the current consumption is prevented in the internal circuit 1.
In the voltage generator circuit 100, when the power-down signal pd rises to H level for a transition from a normal mode to the power-down mode, the transistors Tr2, Tr3 are turned on to reduce the reference voltage Vg and the internal voltage Vdd, as shown in FIG. 3. In this time, since the capacitances of the capacitor C1 and the transistor Tr1 are very large as compared with the driving capability of the transistor Tr2, the reference voltage Vg slowly goes down in accordance with the CR time constant in response to the transistor Tr2 when it turns on. In this situation, in a time period t1 until a potential difference between the reference voltage Vg and the internal voltage Vdd is reduced to the threshold value Vthn of the transistor Tr1 or smaller, the transistors Tr1, Tr3 are simultaneously turned on to cause a through current to flow from the external power supply Vcc to the external power supply Vss. The through current may cause a reduction in voltage of the external power supply Vcc, and a malfunction of the internal circuit 1.
Also, in the voltage generator circuit 100, even if a gate-to-source voltage Vgs of the step-down transistor Tr1 is at 0 V in the power-down mode, a sub-threshold current flows across the drain and source of the transistor Tr1 due to the physical characteristics of the transistor, and this sub-threshold current flows into the external power supply Vss through the transistor Tr3.
When Vgs=0 V, a sub-threshold current IL flowing into an N-channel MOS transistor is generally expressed by the following equation (1):
      I    L    =            Io      Wo        ⁢          W      ·              10                              -            vtc                    /          s                    where W is a channel width of the transistor; Vtc is a gate-to-source voltage when a constant drain-to-source current I0 begins to flow into the transistor having a channel width W0; and S is a tailing coefficient.
For example, a sub-threshold current ranging from several tens to several hundreds of microamperes (μA) flows into the step-down transistor Tr1 having a channel width ranging from several tens to several hundreds of thousands of micrometers (μm), causing increased current consumption in the power-down mode.
FIG. 2 is a schematic circuit diagram of a voltage generator circuit 200 according to a second prior art example. The voltage generator circuit 200 functions as a step-down circuit which includes a plurality of P-channel MOS transistors. A step-down transistor Tr4, comprised of a P-channel MOS transistor, is supplied with a voltage of an external power supply Vcc at a source, and a reference voltage Vg generated by a reference voltage generator circuit at the gate.
The reference voltage Vg is generated by the reference voltage generator circuit such that it rises as an internal voltage Vdd increases and falls as the internal voltage Vdd decreases. Also, the reference voltage Vg is generated such that the internal voltage Vdd is set at a voltage smaller than the voltage of the external power supply Vcc by a predetermined voltage.
The step-down transistor Tr4 has a drain coupled to an internal circuit 1. When the reference voltage Vg is supplied to the gate of the transistor Tr4, the internal circuit 1 is supplied with the internal voltage Vdd.
A reference voltage clamp transistor Tr5, comprised of a P-channel MOS transistor, is coupled between the gate of the transistor Tr4 and the external power supply Vcc. The transistor Tr5 is supplied with a power-down signal pd at the gate through an inverter circuit 2. When the power-down signal pd rises to H level in a power-down mode, the transistor Tr5 is turned on to clamp the reference voltage Vg to the voltage of the external voltage Vcc, causing the transistor Tr4 to turn off.
A capacitor C4 is coupled between the drain of the transistor Tr4 (internal voltage Vdd) and an external power supply Vss. The capacitor C4 is used to stabilize the internal voltage Vdd. The capacitor C4 includes a parasitic capacitance of the internal circuit 1.
An internal voltage clamp transistor Tr6, comprised of an N-channel MOS transistor, is coupled between the drain of the transistor Tr4 and the external power supply Vss. The transistor Tr6 is supplied with the power-down signal pd at the gate. When the power-down signal pd rises to H level, the transistor Tr6 is turned on with the transistor Tr4 remaining off, to clamp the internal voltage Vdd to the voltage of the external power supply Vss, as shown in FIG. 4. Such an operation shuts off the supply of the internal voltage Vdd in the power-down mode, so that the current consumption is prevented in the internal circuit 1.
In the voltage generator circuit 200, as the power-down signal pd rises to H level for a transition from a normal mode to the power-down mode, the transistors Tr5, Tr6 are turned on to increase the reference voltage Vg, causing the internal voltage Vdd to fall down, as shown in FIG. 4. In this event, since the capacitance of the transistor Tr4 is very large as compared with the driving capability of the transistor Tr5, the reference voltage Vg slowly rises in accordance with the CR time constant in response to the transistor Tr5 when it is turned on. Consequently, in a time period t2 until a potential difference between the reference voltage Vg and the voltage of the external power supply Vcc is reduced to a threshold value Vthp of the transistor Tr4 or less, the transistors Tr4, Tr6 are simultaneously turned on, causing a through current to flow from the external power supply Vcc to the external power supply Vss. Therefore, the through current may cause a reduction in voltage of the external power supply Vcc, and a malfunction of the internal circuit 1.
In the voltage generator circuits 100 and 200, if the transistors Tr2, Tr5 are increased in size to improve the current driving capabilities, the reference voltage Vg could be reduced or increased at a higher speed. However, if the transistors Tr2, Tr5 are increased in size so as to ensure load driving capabilities corresponding to the capacitor C1 and the capacitances of the transistors Tr1, Tr4, a resulting increase in circuit area would prevent higher integration.
Also, in the voltage generator circuit 200, even when the gate-to-source voltage Vgs of the step-down transistor Tr4 is at 0 V, the sub-threshold current flows into the transistor Tr4, causing an increase in current consumption.
For example, a voltage generator circuit 200 has been proposed for clamping the internal voltage Vdd to the voltage of the external power supply Vdd in the power-down mode. The voltage generator circuit 200 omits the transistor Tr6 of the step-down circuit of FIG. 2, and turns on the transistor Tr4 in the power-down mode to clamp the internal voltage Vdd to the voltage of the external power supply Vcc. This voltage generator circuit 200 suffers from an increase in current consumption due to a sub-threshold current flowing into a large number of N-channel MOS transistors in an internal circuit 1.